A Buffer-Oriented Methodology for Microarchitecture Validation

We propose a methodology for validating microarchitecture specifications. We view microarchitecture features as specific operations on entries of various buffers in the processor. Our validation approach is to determine the functionality of a buffer type, model its operations at the microarchitecture level using abstract finite state machine (FSM) models, and rigorously generate instruction sequences that systematically exercise the model of each instance of that buffer type. A high-level test sequence is derived based on the abstract FSM model using FSM testing techniques, and then translated to a test program that exercises the functionality of each buffer entry. This methodology is applied to the microarchitecture specifications of the PowerPC 604. The effectiveness of the sequences generated using our methodology is compared with that of some real and randomly-generated programs. Simulation results show that all targeted FSM transitions are covered by our sequences with at least 1000× and 3× fewer instructions than real and randomly-generated programs, respectively.